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atomic: Use __atomic_thread_fence() when available

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This avoids requiring inline assembly for each architecture.

It also fixes some weakly ordered architectures which lacked
said inline assembly (RISC-V, MIPS, LoongArch, etc) and were
thus disasterously broken.

(cherry picked from commit c3b0e62850)
This commit is contained in:
Cameron Gutman 2026-04-23 18:43:44 -05:00
parent f32c6d977c
commit 4bce8906fc
1 changed files with 4 additions and 1 deletions
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5
include/SDL_atomic.h
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@ -174,7 +174,10 @@ extern __inline void SDL_CompilerBarrier(void);
extern DECLSPEC void SDLCALL SDL_MemoryBarrierReleaseFunction(void);
extern DECLSPEC void SDLCALL SDL_MemoryBarrierAcquireFunction(void);
#if defined(__GNUC__) && (defined(__powerpc__) || defined(__ppc__))
#if _SDL_HAS_BUILTIN(__atomic_thread_fence) || (defined(__GNUC__) && (__GNUC__ >= 5))
#define SDL_MemoryBarrierRelease() __atomic_thread_fence(__ATOMIC_RELEASE)
#define SDL_MemoryBarrierAcquire() __atomic_thread_fence(__ATOMIC_ACQUIRE)
#elif defined(__GNUC__) && (defined(__powerpc__) || defined(__ppc__))
#define SDL_MemoryBarrierRelease() __asm__ __volatile__ ("lwsync" : : : "memory")
#define SDL_MemoryBarrierAcquire() __asm__ __volatile__ ("lwsync" : : : "memory")
#elif defined(__GNUC__) && defined(__aarch64__)